The present application claims priority from Korean Patent Application No. 2002-31421, filed Jun. 4, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety.
The present invention relates to methods for manufacturing semiconductor devices and, more particularly, to a method for manufacturing a semiconductor device having an improved quality by increasing an adhesion and improving an interface characteristic between a silicon nitride layer and an oxide layer formed thereon.
Recently, the design of semiconductor devices has experienced rapid progress as information media and devices such as computers are widely used. This progress has required semiconductor devices that can function at high operating speeds and to have large storage capacities. In order to satisfy such requirements, semiconductor devices with increased density, reliability, and response time speed are under development. To increase the degree of integration, the cell size should be reduced and, with the reduction in the cell size, the size and margin of all kinds of patterns formed on a semiconductor substrate also should be reduced. On the other hand, the aspect ratio of each component in the semiconductor device gradually increases.
A polysilicon gate structure having a good electric characteristic, reliability and degree of integration was adopted as a driving device from the initial VLSI. Therefore, the polysilicon gate structure has been largely developed in industrial fields such as LSI""s for micro-computers or devices with high-density memories, and is now widely used in various fields. Because the melting point of polysilicon is high, a self-align method can be applied during the formation of a gate electrode along with a diffusion region of source and drain when using polysilicon. In addition, after patterning the gate electrode using polysilicon, a thermal oxidation of polysilicon may also be performed. Accordingly, damage generated at the edge portion of the gate electrode due to reactive ion etching may be compensated for. When an electric voltage is applied to the gate electrode, a high fringe electric field at the edge portion of the gate electrode is lowered to increase the reliability of the semiconductor device.
Meanwhile, the design rule of recently developed and highly integrated semiconductor devices has been reduced to about 0.15 xcexcm or less. Accordingly, a self-align method is widely used in order to ensure a BC processing margin. A method of forming a contact hole of a semiconductor device by the self-align method will be described in detail below with reference to the attached drawings.
FIGS. 1A-1E are cross-sectional views illustrating a method of forming a contact hole of a semiconductor device in accordance with a conventional method.
Referring to FIG. 1A, a gate oxide layer 21 is formed on a semiconductor substrate 11 such as a silicon substrate. Then, a conductive layer and a capping insulation layer are subsequently formed on the gate oxide layer 21. The conductive layer is a doped polysilicon layer or a polycide layer. The polycide layer includes a doped polysilicon layer and a refractory metal silicide layer. As the refractory metal silicide layer, a tungsten silicide layer, a titanium silicide layer, a cobalt silicide layer, etc., are widely applied.
The capping insulation layer is preferably comprised of silicon nitride. A silicon nitride layer has a high etching selectivity with respect to an oxide layer. Then, the capping insulation layer and the conductive layer are continuously patterned to form parallel gate patterns 37 with a predetermined spacing on a predetermined region of the gate oxide layer 21. Each of the gate patterns 37 includes an integrated conductive layer pattern 31 and a capping insulation layer pattern 32. The conductive layer pattern 31 functions as a gate electrode.
Referring to FIG. 1B, a silicon nitride layer is formed on the entire surface of the substrate on which the gate patterns 37 are formed. Then, the silicon nitride layer is etched anisotropically to form a spacer 33 at the sidewall portions of the gate patterns 37. At this time, the gate oxide layer 21 formed between the gate patterns 37 may be over-etched to expose the semiconductor substrate 11 or such that a thinner oxide layer than the initial gate oxide layer 21 remains. When completing the formation of the spacer 33, the conductive pattern 21, i.e., the gate pattern, is completely surrounded by a gate oxide layer pattern 22, the capping insulation layer pattern 32 and the spacer 33.
During implementation of the anisotropic etching for forming the spacer 33, the surface portion of the semiconductor device is damaged. Therefore, after completing the anisotropic etching to form the spacer 33, a thermal oxidation is performed to remove the etching damage. Then, a thin thermal oxide layer is grown on the surface of the semiconductor substrate 11 between the gate patterns 37. Using the thin thermal oxide layer as a screen oxide layer, ion implantation is conducted to form a source/drain region (not shown) at the surface portion of the semiconductor substrate 11 between the gate patterns 37.
Referring to FIG. 1C, an etching stop layer 34 such as a silicon nitride layer is formed using a chemical vapor deposition (CVD) method. The preferred thickness of the etching stop layer 34 is in a range of from about 70 to about 150 xc3x85. In FIG. 1C, the reference symbol G1 represents a gap size.
Referring to FIG. 1D, an interlayer dielectric 41 is formed on the etching stop layer 34 using an insulating material having a good filling characteristic into a concave portion. Conventionally, a high density plasma CVD oxide layer is formed, or a high density plasma CVD oxide layer and a low pressure CVD oxide layer are subsequently integrated to form the interlayer dielectric.
When the plasma CVD method is applied, the interlayer dielectric adheres to an underlying layer with sufficient adhesive power to prevent separation of the thus formed layer at the interface because the reactivity of the plasma is good. However, as the gap size formed by the etching stop layer becomes narrow, a void is formed. Accordingly, a flow fill method has been used recently instead of the plasma CVD method when the gap size formed between patterns is small.
The method of forming an interlayer dielectric using the flow fill method will be described in detail below. According to this method, a layer is formed by reacting silane with hydrogen peroxide gas utilizing, for example, an apparatus named Flow Fill and manufactured by Trikon Co. Ltd. This method is particularly appropriate for filling a small gap formed between patterns of an underlying layer. Silane compounds such as SiH4, CH3SiH3, etc., are reacted with hydrogen peroxide (H2O2) to produce SiO2 or (SiOCH)n to form a silicon oxide layer. First, the silane compound and hydrogen peroxide are reacted with each other in gaseous phase to produce a hydroxy silane compound such as Si(OH)4 or CH3Si(OH)3. This product generates a liquid phase reaction at the surface portion of the underlying layer to form a polymer though dehydration to deposit an oxide layer of SiO2. Accordingly, when using the flow fill method on a layer having a small pattern gap, the generation of the aforementioned void can be avoided, and so this method is now in wide use.
Next, the interlayer dielectric 41 is planarized. A photoresist pattern 51 having a predetermined shape is formed for patterning the planarized interlayer dielectric.
Referring to FIG. 1E, an interlayer dielectric pattern 42 is formed and the etching stop layer 34 between the gate patterns 37 is exposed by etching the interlayer dielectric 41 using the photoresist pattern 51. Thereafter, the exposed etching stop layer 34 is etched to expose the semiconductor substrate 11 between the gate patterns 37 to form a self-aligned contact hole.
According to the above-described conventional flow fill method, the hydrophilic monomers Si(OH)4, CH3Si(OH)3, etc., flow into the gap and achieve a good adhesion with the underlying silicon nitride layer during the deposition of the starting material to form the interlayer dielectric. Reaction at the interface during the flow fill method will be described in detail with reference to FIGS. 2A and 2B. As the starting material, CH3Si(OH)3 and H2O2 may be used. The symbol M in the drawings represents CH3.
Referring to FIG. 2A, the surface reaction on the substrate is illustrated through a reaction between methyl silane and hydrogen peroxide. As the reaction of methyl silane and hydrogen peroxide proceeds, the hydrogen bonds in the methyl silane are replaced one by one with hydroxy bonds.
Referring to FIG. 2B, one molecule of water is removed from one pair of neighboring CH3Si(OH)3 compounds to make a bond through the medium of an oxygen atom between them. This reaction progresses continuously to accomplish the polymerization and to form a silicon oxide layer. When methyl silane is used as the starting material, an oxide layer including a basic unit of (SiOCH)n (n represents a positive integer) is formed.
Because the substrate is formed of SiN and has a low hydrophilicity, the hydrophilic monomer formed during the deposition by the flow fill method, that is, CH3Si(OH)3, does not sufficiently flow into the small gap and does not sufficiently adhere with the underlying layer. As a result, this hydrophilic monomer comes off at the interface with the underlying layer during an annealing process that is implemented after completing the deposition. In order to address the above-described problem, a plasma treatment using N2O, O2, etc., is performed after forming the SiN layer.
FIGS. 3A and 3B are cross-sectional views for comparing the adhesion characteristics at the interface when the N2O plasma treatment is implemented or not, after forming the SiN layer. The construction of FIG. 3A is obtained when the plasma treatment is not implemented after forming the SiN layer and the construction of FIG. 3B is obtained when the N2O plasma treatment is implemented after forming the SiN layer. In the drawings, the portion designated by hatched lines at the interface of a nitride layer and an oxide layer indicates a portion that has come off at the interface.
When comparing the two drawings, it may be noted that the adhesion characteristic at the interface of the nitride layer and the oxide layer is better when the plasma treatment is implemented than when the plasma treatment is not implemented. It is believed that this improvement at the interface by the plasma treatment is obtained because a thin oxide layer is formed on the surface of the SiN layer by the plasma treatment and, as the result, the adhesion of the SiN layer with the material produced during the flow fill method is improved.
However, after completing the plasma treatment, small clefts at the interface are still found as a defect. Because the plasma has an anisotropy, the side portion of the gap between the patterns is not sufficiently treated to prevent the generation of some defects, especially when the gap is small.
Japanese Patent Laid-Open Publication No. Hei 9-162291 discloses a method of preventing the generation of a defect at an interface of a nitride layer and an interlayer dielectric. An insulating layer is formed by a plasma CVD method. The thus formed insulating layer is exposed to an ArF excimer laser and an ammonia gas is introduced to form nitride on the surface of the insulating layer. Then, an SOG insulating layer is formed on the layer on which the nitride is formed.
According to this method, an etching stop layer having a uniform thickness can be formed on the thus obtained layer on which the nitride layer is formed. When a high density plasma CVD oxide layer is formed on the etching stop layer, the etching stop layer can be prevented from coming off. However, this method is somewhat complicated and is difficult to perform when an oxide layer is formed as an insulating layer by the flow fill method.
According to method embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.
According to further method embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The hydrophilicity of a surface of the silicon nitride layer is increased. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.
According to further method embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a gate pattern on a semiconductor substrate. A spacer is formed on a side wall portion of the gate pattern. A silicon nitride layer is formed, the silicon nitride layer including a plurality of bonds formed between silicon and nitrogen. A portion of the bonds between silicon and nitrogen is broken to form free bonding sites on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.
Objects of the present invention will be appreciated by those of ordinary skill in the art from a reading of the figures and the detailed description of the preferred embodiments which follow, such description being merely illustrative of the present invention.